Interface substrate and method of making the same

ABSTRACT

A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold compound. In one example, the package may be a wafer level package that allows an external connection on the backside of the package to enable manufacturing in a panel or wafer form.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application for patent claims the benefit of U.S.Provisional Patent Application No. 62/333,038, entitled “INTERFACESUBSTRATE AND METHOD OF MAKING THE SAME,” filed May 6, 2016, pending,assigned to the assignee hereof, and expressly incorporated herein byreference in its entirety.

The present application for patent is a continuation of patentapplication Ser. No. 15/256,501 entitled “INTERFACE SUBSTRATE AND METHODOF MAKING THE SAME” filed Sep. 2, 2016, pending, assigned to theassignee hereof, and expressly incorporated by reference in itsentirety.

FIELD OF DISCLOSURE

This disclosure relates generally to substrates, and more specifically,but not exclusively, to wafer level package substrates.

BACKGROUND

Conventional wafer level package (WLP) use photo-dielectric material forlayer to layer passivation and connection. However, photo-dielectricmaterial is a thinner and physically weaker material than that used forsubstrate cores. In addition, conventional substrate based and leadframebased packages are bigger in size than semiconductor dies coupled to theWLPs. This creates a problem when the package size is critical, such aswhen the package size must be the same as the semiconductor die coupledto the package. In addition, certain sensor applications requirealternative interconnection methods than can be provided with a WLPsince the materials and processes used would impact the performance ofthe sensing components.

Accordingly, there is a need for systems, apparatus, and methods thatovercome the deficiencies of conventional approaches including themethods, system and apparatus provided hereby.

SUMMARY

The following presents a simplified summary relating to one or moreaspects and/or examples associated with the apparatus and methodsdisclosed herein. As such, the following summary should not beconsidered an extensive overview relating to all contemplated aspectsand/or examples, nor should the following summary be regarded toidentify key or critical elements relating to all contemplated aspectsand/or examples or to delineate the scope associated with any particularaspect and/or example. Accordingly, the following summary has the solepurpose to present certain concepts relating to one or more aspectsand/or examples relating to the apparatus and methods disclosed hereinin a simplified form to precede the detailed description presentedbelow.

In one aspect, a semiconductor package comprises: a semiconductor die; asubstrate; a mold compound configured to encapsulate the substrate; afirst plurality of pads on a first side of the substrate; a plurality offirst contacts on the first plurality of pads; a second plurality ofpads on a second side of the substrate; a plurality of second contactson the second plurality of pads, the plurality of second contactscoupled to the semiconductor die; a plurality of interconnects 180 thatextend from the first plurality of pads to the second plurality of pads;and a redistribution layer embedded in the substrate proximate thesecond side of the substrate.

In another aspect, a sensor package comprises: a sensor configured toreceive an input and transmit an output; a thin film transistorconnected to the sensor; a piezoelectric layer on a first side of thethin film transistor opposite the sensor; a first metal layer configuredto encapsulate the piezoelectric layer; a first mold compound configuredto encapsulate the first metal layer; a second metal layer proximate tothe first metal layer; a conductive layer proximate to the second metallayer; a substrate connected to the conductive layer opposite the secondmetal layer; and an external connection coupled to the substrateopposite the conductive layer.

In still another aspect, a method for forming a semiconductor packagecomprises: forming a plurality of substrates, each of the plurality ofsubstrates has a first width; forming a plurality of semiconductor dieson the wafer, each of the plurality of semiconductor dies has a secondwidth larger than the first width; placing the plurality of substrateson the plurality of semiconductor dies; attaching each of the pluralityof substrates to a corresponding one of the plurality of semiconductordies; applying a mold compound to the wafer, the mold compoundconfigured to encapsulate the plurality of substrates; and singulatingthe wafer to form a plurality of semiconductor packages, each of theplurality of semiconductor packages comprises one of the plurality ofsubstrates and one of the plurality of semiconductor dies and each ofthe plurality of semiconductor packages has a third width approximatelyequal to the second width.

Other features and advantages associated with the apparatus and methodsdisclosed herein will be apparent to those skilled in the art based onthe accompanying drawings and detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of aspects of the disclosure and many ofthe attendant advantages thereof will be readily obtained as the samebecomes better understood by reference to the following detaileddescription when considered in connection with the accompanying drawingswhich are presented solely for illustration and not limitation of thedisclosure, and in which:

FIG. 1 illustrates an exemplary semiconductor package structure inaccordance with some examples of the disclosure.

FIG. 2 illustrates an exemplary sensor application of a substrate inaccordance with some examples of the disclosure.

FIGS. 3A-D illustrate an exemplary method for fabrication of a WLP witha substrate in accordance with some examples of the disclosure.

FIG. 4 illustrates an exemplary method for fabrication of a WLP inaccordance with some examples of the disclosure.

FIG. 5 illustrates various electronic devices that may be integratedwith any of the aforementioned interface substrate, integrated device,semiconductor device, integrated circuit, die, interposer, package orpackage-on-package (PoP) in accordance with some examples of thedisclosure.

In accordance with common practice, the features depicted by thedrawings may not be drawn to scale. Accordingly, the dimensions of thedepicted features may be arbitrarily expanded or reduced for clarity. Inaccordance with common practice, some of the drawings are simplified forclarity. Thus, the drawings may not depict all components of aparticular apparatus or method. Further, like reference numerals denotelike features throughout the specification and figures.

DETAILED DESCRIPTION

The exemplary methods, apparatus, and systems disclosed herein addressthe industry needs, as well as other previously unidentified needs, andmitigate shortcomings of the conventional methods, apparatus, andsystems. For example, an interface substrate according to some examplesof the disclosure may include a thinner, smaller interface substrateassembly that is equal to or smaller in size than a semiconductor diecoupled to the assembly. In another example, an interface substrateassembly process may use conventional die bonding and reflow processesor laser assist bonding to manufacture the thinner, smaller interfacesubstrate assembly. This may allow the interface substrate to replace aconventional redistribution layer (RDL) manufacturing process so thatknown-good substrates can be assembled with semiconductor dies tominimize die loss and substrate loss. Furthermore, an interfacesubstrate package may be molded to increase the assembly reliability andball reliability better than WLPs. Benefits of the examples describedherein include processing in wafer form that allows a higher throughputprocess than conventional individual and strip based structures,manufacturing process may use conventional wafer handling infrastructurewithout the need for a RDL process step, may provide a more robustnesspackage for low k wafer nodes, a packaged part may have the same formfactor as a WLP, may provide an interconnection with the packagebackside for applications (such as sensor applications) where part ofthe package surface needs to be free of other materials thus avoidingsingle unit processing necessitated by interconnections on the side ofthe package, and minimize manufacturing process costs and failure costsby using known-good substrates and known-good die assemblies in thepackage.

FIG. 1 illustrates an exemplary semiconductor package structure inaccordance with some examples of the disclosure. As shown in FIG. 1, asemiconductor package 100 (e.g. a wafer level chip scale package) mayinclude a semiconductor die 110 (e.g. a logic die, memory die, orintegrated circuit), a substrate 120, and a mold compound 130encapsulating the substrate 120. The semiconductor die has an outerperimeter 112 shown with dashed lines in FIG. 1 and a width 114. Thesubstrate 120 may include a first sidewall 121, a second sidewall 123, afirst plurality of pads 140 on a first side 122 of substrate 120opposites a second side 124 of the substrate 120, a plurality of firstcontacts 150 (e.g. solder bumps or solder balls) on the first pluralityof pads 140 for enabling an external connection (not shown), a secondplurality of pads 160 on the second side 124, a plurality of secondcontacts 170 (e.g. solder bumps or solder balls) on the second pluralityof pads 160 for enabling connection to the semiconductor die 110, aplurality of interconnects 180 (e.g. copper pillars or electricallyconductive vias) extending from the first plurality of pads 140 to thesecond plurality of pads 160 for connecting the first plurality of pads140 to the second plurality of pads 160, and a redistribution layer 190embedded in the substrate 120 near the second side 124. The substrate120 may be composed of ceramic and/or organic materials, for example,and may have a smaller width than the semiconductor die 110. The moldcompound 130 may encapsulate the substrate 120 only with a width 132sized to match the width 114 of the semiconductor die 110 such that thesemiconductor package 100 has the same width as the semiconductor die110 and the sidewalls 121 and 123 of the substrate 120 are not exposed.

FIG. 2 illustrates an exemplary sensor application of a substrate inaccordance with some examples of the disclosure. As shown in FIG. 2, asensor package 200 may include a platen 210 (e.g. for a finger printsensor), a thin film transistor (TFT) 220 (e.g. a silicon TFT) connectedto the platen 210, a piezoelectric layer 230, a first metal layer 240(e.g. a copper layer), a mold compound 250, a second metal layer 260(e.g. a copper layer), a conductive layer 270 (e.g. anisotropicconductive film (ACF) or solder), and the substrate package 100 with anexternal connection 280 on a backside 201 of the sensor package 200.This will allow wafer level processing because the external connection280 does not extend to either side of the package and will not becompromised by a singulation process of the wafer. The TFT 220,piezoelectric layer 230 and the first metal layer 240 comprise an activecircuitry area of the sensor 210 and are located on one side of thesensor package 200 opposite the semiconductor package 100. This willallow the active circuitry area to be separate from the semiconductorpackage 100 without interference or loss of area under the sensor 210.The piezoelectric layer 230 may comprise, for example, piezoelectricmaterials that may be employed according to various implementationsinclude piezoelectric polymers having appropriate acoustic properties.For example, an acoustic impedance between about 2.5 MRayls and 5MRayls. Specific examples of piezoelectric materials that may beemployed include ferroelectric polymers such as polyvinylidene fluoride(PVDF) and polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE)copolymers. Examples of PVDF copolymers include 60:40 (molar percent)PVDF-TrFE, 70:30 PVDF-TrFE, 80:20 PVDF-TrFE, and 90:10 PVDR-TrFE. Otherexamples of piezoelectric materials that may be employed include Teflon®and other PTFE polymers, polyvinylidene chloride (PVDC) homopolymers andcopolymers, polytetrafluoroethylene (PTFE) homopolymers and copolymers,and diisopropylammonium bromide (DIPAB).

FIGS. 3A-D illustrate an exemplary method for fabrication of a WLP witha substrate in accordance with some examples of the disclosure. As shownin FIG. 3A, a substrate 120 is formed. The substrate 120 may be one ofseveral configurations depending on the intended application. Forexample, a substrate 120A may include the first plurality of pads 140 onthe first side 122 of substrate 120A opposites the second side 124 ofthe substrate 120A, the second plurality of pads 160 on the second side124, the plurality of second contacts 170 (e.g. solder bumps or solderballs) on the second plurality of pads 160, and the plurality ofinterconnects 180 extending from the first plurality of pads 140 to thesecond plurality of pads 160 for connecting the first plurality of pads140 to the second plurality of pads 160, and the redistribution layer190 embedded in the substrate 120A. In another example, a substrate 120Bmay include the first plurality of pads 140 on the second plurality ofpads 160, and the plurality of interconnects 180 extending from thefirst plurality of pads 140 to the second plurality of pads 160 forconnecting the first plurality of pads 140 to the second plurality ofpads 160 and the redistribution layer 190. In yet another example, asubstrate 120C may include the first plurality of pads 140, theplurality of first contacts 150 (e.g. solder bumps or solder balls) onthe first plurality of pads 140, the second plurality of pads 160, theplurality of second contacts 170 (e.g. solder bumps or solder balls) onthe second plurality of pads 160, the plurality of interconnects 180extending from the first plurality of pads 140 to the second pluralityof pads 160 for connecting the first plurality of pads 140 to the secondplurality of pads 160, and the redistribution layer 190. Next in FIG.3B, a wafer 300 is formed with appropriate surface finish and/or padstack. The wafer 300 may include a plurality of semiconductor dies 310(e.g. semiconductor die 110) and, as in this example, a plurality ofsecond contacts 170 for each of the corresponding plurality ofsemiconductor dies 310.

Next in FIG. 3C, a plurality of substrates 120A, for example, are placedon a corresponding one of the plurality of semiconductor dies 310 and asolder reflow process is applied to connect one of the plurality ofsubstrates 120A to a corresponding one of the plurality of semiconductordies 310. Alternatively, a curing process may be used to connect one ofthe plurality of substrates 120A to a corresponding one of the pluralityof semiconductor dies 310 if a ACF layer is used instead of theplurality of second contacts 170. Next in FIG. 3D, a wafer level moldcompound 330 is applied to encapsulate the plurality of substrates 120Asuch that the plurality of semiconductor dies 310 are free of moldcompound 330. Then, an optional pad cleaning process may be applied thewafer 300 if desired and an optional solder ball attachment process maybe applied to the plurality of substrates 120A for a ball grid array(BGA) application, for instance, or an optional organic solderabilityprotectant (OSP) may be added for a land grid array (LGA) application.Last, the wafer 300 may be singulated to form individual semiconductorpackages 100.

FIG. 4 illustrates an exemplary method for fabrication of a WLP inaccordance with some examples of the disclosure. As shown in FIG. 4, amethod for forming a semiconductor package begins in block 410 withforming a plurality of substrates, each of the plurality of substrateshas a first width. Next in block 420, the method continues with forminga plurality of semiconductor dies on a wafer, each of the plurality ofsemiconductor dies has a second width larger than the first width. Nextin block 430, the method continues with placing the plurality ofsubstrates on the plurality of semiconductor dies. Next in block 440,the method continues with attaching each of the plurality of substratesto a corresponding one of the plurality of semiconductor dies. Next inblock 450, the method continues with applying a mold compound to thewafer, the mold compound configured to encapsulate the plurality ofsubstrates. Next in block 460, the method concludes with singulating thewafer to form a plurality of semiconductor packages, each of theplurality of semiconductor packages comprises one of the plurality ofsubstrates and one of the plurality of semiconductor dies and each ofthe plurality of semiconductor packages has a third width approximatelyequal to the second width.

FIG. 5 illustrates various electronic devices that may be integratedwith any of the aforementioned substrates, integrated device,semiconductor device, integrated circuit, die, interposer, package orpackage-on-package (PoP) in accordance with some examples of thedisclosure. For example, a mobile phone device 502, a laptop computerdevice 504, and a fixed location terminal device 506 may include anintegrated device 500 as described herein. The integrated device 500 maybe, for example, any of the integrated circuits, dies, integrateddevices, integrated device packages, integrated circuit devices, devicepackages, integrated circuit (IC) packages, package-on-package devicesdescribed herein. The devices 502, 504, 506 illustrated in FIG. 5 aremerely exemplary. Other electronic devices may also feature theintegrated device 500 including, but not limited to, a group of devices(e.g., electronic devices) that includes mobile devices, hand-heldpersonal communication systems (PCS) units, portable data units such aspersonal digital assistants, global positioning system (GPS) enableddevices, navigation devices, set top boxes, music players, videoplayers, entertainment units, fixed location data units such as meterreading equipment, communications devices, smartphones, tabletcomputers, computers, wearable devices, servers, routers, electronicdevices implemented in automotive vehicles (e.g., autonomous vehicles),or any other device that stores or retrieves data or computerinstructions, or any combination thereof.

One or more of the components, processes, features, and/or functionsillustrated in FIGS. 1, 2, 3A-D, 4 and/or 5 may be rearranged and/orcombined into a single component, process, feature or function orembodied in several components, processes, or functions. Additionalelements, components, processes, and/or functions may also be addedwithout departing from the disclosure. It should also be noted thatFIGS. 1, 2, 3A-D, 4 and/or 5 and its corresponding description in thepresent disclosure is not limited to dies and/or ICs. In someimplementations, FIGS. 1, 2, 3A-D, 4 and/or 5 and its correspondingdescription may be used to manufacture, create, provide, and/or produceintegrated devices. In some implementations, a device may include a die,an integrated device, a die package, an integrated circuit (IC), adevice package, an integrated circuit (IC) package, a wafer, asemiconductor device, a package on package (PoP) device, and/or aninterposer.

In this description, certain terminology is used to describe certainfeatures. The term “mobile device” can describe, and is not limited to,a music player, a video player, an entertainment unit, a navigationdevice, a communications device, a mobile device, a mobile phone, asmartphone, a personal digital assistant, a fixed location terminal, atablet computer, a computer, a wearable device, a laptop computer, aserver, an automotive device in an automotive vehicle, and/or othertypes of portable electronic devices typically carried by a personand/or having communication capabilities (e.g., wireless, cellular,infrared, short-range radio, etc.). Further, the terms “user equipment”(UE), “mobile terminal,” “mobile device,” and “wireless device,” can beinterchangeable.

The wireless communication between electronic devices can be based ondifferent technologies, such as code division multiple access (CDMA),W-CDMA, time division multiple access (TDMA), frequency divisionmultiple access (FDMA), Orthogonal Frequency Division Multiplexing(OFDM), Global System for Mobile Communications (GSM), 3GPP Long TermEvolution (LTE) or other protocols that may be used in a wirelesscommunications network or a data communications network.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration.” Any details described herein as “exemplary”is not to be construed as advantageous over other examples. Likewise,the term “examples” does not mean that all examples include thediscussed feature, advantage or mode of operation. Furthermore, aparticular feature and/or structure can be combined with one or moreother features and/or structures. Moreover, at least a portion of theapparatus described hereby can be configured to perform at least aportion of a method described hereby.

The terminology used herein is for the purpose of describing particularexamples and is not intended to be limiting of examples of thedisclosure. As used herein, the singular forms “a,” “an,” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising,” “includes,” and/or “including,” when usedherein, specify the presence of stated features, integers, actions,operations, elements, and/or components, but do not preclude thepresence or addition of one or more other features, integers, actions,operations, elements, components, and/or groups thereof.

It should be noted that the terms “connected,” “coupled,” or any variantthereof, mean any connection or coupling, either direct or indirect,between elements, and can encompass a presence of an intermediateelement between two elements that are “connected” or “coupled” togethervia the intermediate element.

Any reference herein to an element using a designation such as “first,”“second,” and so forth does not limit the quantity and/or order of thoseelements. Rather, these designations are used as a convenient method ofdistinguishing between two or more elements and/or instances of anelement. Also, unless stated otherwise, a set of elements can compriseone or more elements.

Nothing stated or illustrated depicted in this application is intendedto dedicate any component, action, feature, benefit, advantage, orequivalent to the public, regardless of whether the component, action,feature, benefit, advantage, or the equivalent is recited in the claims.

In the detailed description above it can be seen that different featuresare grouped together in examples. This manner of disclosure should notbe understood as an intention that the claimed examples have morefeatures than are explicitly mentioned in the respective claim. Rather,the situation is such that inventive content may reside in fewer thanall features of an individual example disclosed. Therefore, thefollowing claims should hereby be deemed to be incorporated in thedescription, wherein each claim by itself can stand as a separateexample. Although each claim by itself can stand as a separate example,it should be noted that—although a dependent claim can refer in theclaims to a specific combination with one or a plurality of claims—otherexamples can also encompass or include a combination of said dependentclaim with the subject matter of any other dependent claim or acombination of any feature with other dependent and independent claims.Such combinations are proposed herein, unless it is explicitly expressedthat a specific combination is not intended. Furthermore, it is alsointended that features of a claim can be included in any otherindependent claim, even if said claim is not directly dependent on theindependent claim.

It should furthermore be noted that methods disclosed in the descriptionor in the claims can be implemented by a device comprising means forperforming the respective actions of this method.

Furthermore, in some examples, an individual action can be subdividedinto a plurality of sub-actions or contain a plurality of sub-actions.Such sub-actions can be contained in the disclosure of the individualaction and be part of the disclosure of the individual action.

While the foregoing disclosure shows illustrative examples of thedisclosure, it should be noted that various changes and modificationscould be made herein without departing from the scope of the disclosureas defined by the appended claims. The functions and/or actions of themethod claims in accordance with the examples of the disclosuredescribed herein need not be performed in any particular order.Additionally, well-known elements will not be described in detail or maybe omitted so as to not obscure the relevant details of the aspects andexamples disclosed herein. Furthermore, although elements of thedisclosure may be described or claimed in the singular, the plural iscontemplated unless limitation to the singular is explicitly stated.

What is claimed is:
 1. A package comprising: a semiconductor die with aperimeter defined by sidewalls and a width; a package substrate withsidewalls, the package substrate located vertically below thesemiconductor die within the perimeter; a mold compound with sidewallsand a width configured to encapsulate the package substrate, the moldcompound width is approximately the same as the semiconductor die widthand each sidewall of the mold compound is co-planar with a respectivesidewall of the semiconductor die; a first plurality of pads on a firstside of the package substrate; a second plurality of pads on a secondside of the package substrate; a plurality of interconnects that extendfrom the first plurality of pads to the second plurality of pads; and aredistribution layer embedded in the package substrate proximate thesecond side of the package substrate and embedded in the mold compoundwherein the second side of the package substrate faces the semiconductordie.
 2. The package of claim 1, wherein the sidewalls of the packagesubstrate are not exposed and the package substrate is completelyunderneath the semiconductor die.
 3. The package of claim 1, wherein themold compound is completely underneath the semiconductor die within theperimeter of the semiconductor die.
 4. The package of claim 1, furthercomprising: a plurality of first contacts on the first plurality ofpads; and a plurality of second contacts on the second plurality ofpads, the plurality of second contacts coupled to the semiconductor die.5. The package of claim 4, wherein the plurality of first contacts aresolder bumps or solder balls and the plurality of second contacts aresolder bumps or solder balls.
 6. The package of claim 1, wherein theplurality of interconnects are copper pillars or conductive vias.
 7. Thepackage of claim 1, wherein the sidewalls of the package substrate areparallel to sidewalls of the mold compound.
 8. The package of claim 1,wherein the package is incorporated into a device selected from a groupconsisting of a music player, a video player, an entertainment unit, anavigation device, a communications device, a mobile device, a mobilephone, a smartphone, a personal digital assistant, a fixed locationterminal, a tablet computer, a computer, a wearable device, a laptopcomputer, a server, and a device in an automotive vehicle, and furtherincluding the device.
 9. The package of claim 1, wherein the moldcompound includes a width sized to approximately match the semiconductordie width.
 10. The package of claim 1, wherein the package substrate issmaller in size than the semiconductor die.
 11. A method for forming apackage, comprising: forming a plurality of substrates, each of theplurality of substrates has a first width; forming a plurality ofsemiconductor dies on a wafer, each of the plurality of semiconductordies has a second width larger than the first width; placing theplurality of substrates on the plurality of semiconductor dies;attaching each of the plurality of substrates to a corresponding one ofthe plurality of semiconductor dies; applying a mold compound to thewafer, the mold compound configured to encapsulate the plurality ofsubstrates, wherein each semiconductor die has a perimeter defined bysidewalls and a width, each substrate has sidewalls and is verticallybelow one of the plurality of semiconductor dies within the perimeter,and the mold compound has sidewalls and a width configured toencapsulate one of the plurality of substrates and is approximately thesame as the semiconductor die width and each sidewall of the moldcompound is co-planar with a respective sidewall of the semiconductordie; and singulating the wafer to form a plurality of packages, each ofthe plurality of packages comprises one of the plurality of substratesand one of the plurality of semiconductor dies and each of the pluralityof packages has a third width approximately equal to the second width.12. The method of claim 11, wherein the forming each of the plurality ofsubstrates comprises: forming a plurality of interconnects that extendfrom a first side of the substrate to a second side of the substrateopposite the first side of the substrate; forming a redistribution layerembedded in the substrate proximate the second side of the substrate;forming a first plurality of pads on the first side of the substrate,the first plurality of pads connected to the plurality of interconnects;forming a plurality of first contacts on the first plurality of pads;forming a second plurality of pads on the second side of the substrate,the second plurality of pads connected to the plurality ofinterconnects; forming a plurality of second contacts on the secondplurality of pads; and applying a mold compound configured toencapsulate the substrate.
 13. The method of claim 12, wherein sidewallsof each of the plurality of substrates are not exposed.
 14. The methodof claim 12, wherein each of the plurality of substrates is completelyunderneath a corresponding one of the plurality of semiconductor dies.15. The method of claim 12, wherein, after the singulating, the moldcompound is completely underneath each of the plurality of semiconductordies within a perimeter of each of plurality of semiconductor dies. 16.The method of claim 12, wherein the plurality of first contacts aresolder bumps or solder balls and the plurality of second contacts aresolder bumps or solder balls.
 17. The method of claim 12, wherein theplurality of interconnects are copper pillars or conductive vias. 18.The method of claim 12, wherein each of the plurality of substrates iscomposed of ceramic or organic materials.
 19. The method of claim 12,wherein at least one of the plurality of packages is incorporated into adevice selected from a group consisting of a music player, a videoplayer, an entertainment unit, a navigation device, a communicationsdevice, a mobile device, a mobile phone, a smartphone, a personaldigital assistant, a fixed location terminal, a tablet computer, acomputer, a wearable device, a laptop computer, a server, and a devicein an automotive vehicle, and further including the device.
 20. Themethod of claim 11, wherein the attaching each of the plurality ofsubstrates to the corresponding one of the plurality of semiconductordies comprises a solder reflow process or a curing process.